// +FHDR------------------------------------------------------------
//                 Copyright (c) 2024 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : async_1bit_delay.v
// Author        : ICer
// Created On    : 2024-03-14 11:16
// Last Modified : 2024-03-14 12:05 by ICer
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------


module async_1bit_delay #(
  parameter DL = 2,
  parameter FF = 1
)( /*AUTOARG*/
   // Inputs
   i_clk, i_rst_n, i_data, o_clk, o_rst_n, o_data
   );

// ----------------------------------------------------------------
// Interface declare
// ----------------------------------------------------------------
input  i_clk;
input  i_rst_n;
input  i_data;

input  o_clk;
input  o_rst_n;
output o_data;

// ----------------------------------------------------------------
// i_clk pipe
// ----------------------------------------------------------------
wire i_data_in;
generate
  if(FF == 0)begin: NO_IN_DFF
    assign i_data_in = i_data;
  end //if(FF == 0)begin: NO_IN_DFF
  else begin: IN_DFF
    reg i_data_ff;
    always @(posedge i_clk or negedge i_rst_n) begin
      if(!i_rst_n)
        i_data_ff <= 1'b0;
      else
        i_data_ff <= i_data;
    end
    assign i_data_in = i_data_ff;
  end //else begin: IN_DFF
endgenerate

// ----------------------------------------------------------------
// o_clk pipe
// ----------------------------------------------------------------
reg [DL -1:0]o_data_ff;
integer i;
always @(posedge o_clk or negedge o_rst_n) begin
  if(!o_rst_n) begin
    o_data_ff <= {DL{1'b0}};
  end
  else begin
    o_data_ff[0] <= i_data_in;
    for(i=1; i<DL; i=i+1)begin
      o_data_ff[i] <= o_data_ff[i-1];
    end
  end
end

assign o_data = o_data_ff[DL-1];

endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:

